1. Field of the Invention
The present invention relates to a magnetic recording apparatus for generating, by a magnetic head, a magnetic field corresponding to data intended to record, and for recording the data on a recording medium by the generated magnetic field.
2. Description of the Related Art
Recently, in the magnetic recording apparatus such as a hard disk apparatus, the recording density has rapidly increased, and the writing speed has also increased.
In the magnetic recording apparatus, the writing of data is performed by reversing the direction of the current flowing through a magnetic head coil positioned close to a recording medium on which the writing is to be made, in accordance with the data to be recorded.
FIG. 10 shows an outline of a magnetic head driving circuit of a magnetic recording apparatus (STEVE, L., DAVID, Y., “A 550 MB/S GMR READ/WRITE AMPLIFIER USING 0.5 UM 5V CMOS PROCESS”, ISSCC2000, PP358-359, FEBRUARY, 2000). In FIG. 10, the magnetic head driving circuit is formed by PMOS transistors MP1, MP2, and NMOS transistors MN7 to MN10 which operate as switches, NMOS transistors MN1, MN2, and PMOS transistors MP3, MP4 which operate as protection devices, and a current mirror circuit including NMOS transistors MN3 to MN7, MN10, and a current source IS1, and a DAMPING-RESISTOR circuit. This circuit is operated at a timing shown in FIG. 11, and each transistor and the DAMPING-RESISTOR circuit are controlled. A magnetic head coil is formed by an inductance component Lh and a resistance component Rh. At a time t1, by turning off the PMOS transistor MP1 and the NMOS transistor MN10 which have been turned on, and at the same time, by turning on the PMOS transistor MP2 and the NMOS transistor MN7 which have been turned off, the current which has been flowing in the magnetic head coil from a node HWL towards a node HWR is reversed to flow from the node HWR towards the node HWL, at this time due to the turning on of the NMOS transistor MN8 only during a time interval until a time t2, a large voltage (here, the power supply voltage) is applied across both terminals of the magnetic head coil so that the reverse time of the current is shortened. Next, from the time t2 to the time t3, assuming that the current flowing in the current source IS1 is IW1, in the magnetic head coil, a constant current IW1 flows from the node HWR towards the node HWL. Next, at the time t3, the PMOS transistor MP2 and the NMOS transistor MN7 which have been turned on are turned off, and at the same time, the PMOS transistor MP1 and the NMOS transistor MN10 which have been turned off are turned on, so that the current which has been flowing in the magnetic head coil from the node HWR towards the node HWL is reversed to flow from the node HWL towards the node HWR. At this time, since the NMOS transistor MN9 is turned on only until the time t4, similar to the time period between the time t2 and the time t3, a large voltage (here, the power supply voltage) is applied in a reverse direction to the case mentioned above across both terminals of the magnetic head coil, and the reverse time of the current is shortened. During the time period between the time t4 and the time t5, a current IW1 flows from the node HWL towards the node HWR, and thereafter from the time t5, performs the operation from the time t1 repeatedly. Here, in the circuit described above, the problems mentioned below are supposed.
First, as a first problem, in recent years, there is a trend that the power supply voltage of the integrated circuits becomes lower than the withstand voltage of the transistors due to the fact that the device is made smaller, and the operating speed is made faster, and recently, it is 3V to 5V or lower. In the magnetic head driving circuit described in the foregoing, when the power supply voltage becomes low, the time required for reversing the current of the magnetic head coil increases. Furthermore, due to an increase of the data transfer speed accompanied by a large capacity of recent magnetic disk apparatus, further high speed rise/fall is requested, and in order to realize the high speed rise/fall with the above-mentioned magnetic head driving circuit, the power supply voltage must be increased. However, in the case of considering the withstand voltage of the device, it is necessary to insert at many stages the protection devices such as the transistors MP3, MP4, MN1, and MN2, and then in turn, the on-resistances of the protection devices can not be neglected. In order to decrease the on-resistance, it is necessary to increase the size of the protection devices. In particular, in the integrated circuits, the chip size, and the parasitic capacitance are increased, and this raises a problem in view of the economy and the switching speed.
Next, in recent years, there is a trend that the distance between the magnetic head and the recording medium is reduced (several tens of nm), and it is desired that the central potential of the magnetic head coil is stable near the disk potential from the view point of discharge prevention between the magnetic head and the disk. However, in the present circuit, assuming that the current flowing in the current source IS1 is IW1, the resistance of the magnetic head coil RH≈0, and the on-resistance of each transistor is; RMP1=RMP2=RPON1, RMP3=RMP4=RPON2, RMN1=RMN2=RNON1, RMN8=RMN9=RNON2, at the time t1, the central potential VHC of the magnetic head coil is changed from VCC−IW1×(RPON1+RPON2) to VCC×(RPON1+RNON2)/(RPON1+RPON2+RNON1+RNON2) potential, and at the time t2, returns to VCC−IW1×(RPON1+RPON2). Here, since each transistor MP1 to MP4, MN1, MN2, MN7, MN8 is a switch and a protection device, assuming that its on-resistance is sufficiently small and equal, ultimately, the central potential of the magnetic head coil becomes approximately VCC→VCC/2→VCC as shown in FIG. 11. Also, at times t3, and t4, a similar change is exhibited, and there is also a problem that at the time of reversal of the direction of the magnetic head coil current, the central potential of the magnetic head coil is varied to a great extent.